The present invention is related to clock and data recovery from digital data signals, and more specifically to a method and apparatus for detection of the phase difference between a data signal and a local clock and for phase aligning the data signal and local clock.
In order to recover data from a transmitted digital data signal, it is desirable to match the frequency of a local clock with the frequency of the data signal and align the local clock with the incoming data stream in a predetermined phase relationship. This phase relationship is chosen to minimize the chance of error during data recovery due to such phenomenon as jitter. This may be accomplished by detecting the phase difference between the transmitted data signal and a local clock and using the detected phase difference to properly align the data stream with a local clock. For example, it may be desirable to align the rising edge of a local clock with the center of an incoming data bit. A properly aligned data signal and clock are considered phase-locked.
FIG. 1 illustrates a prior art phase detector commonly known as the Hogge detector. The Hogge detector is described in U.S. Pat. No. 4,535,459 to Hogge, Jr., the entirety of which is incorporated herein by reference. The Hogge detector 10 includes two data latches 12, 14 that are D flip-flops. The detector 10 generates a variable width pulse signal UP at exclusive OR gate 16 and a reference pulse DOWN at exclusive OR gate 18. The width of the UP pulse indicates whether a local oscillator generating the local clock signal must change phase to align itself with an input data stream.
FIG. 5 is a timing diagram for the Hogge detector. The waveforms of FIG. 5 are labeled to correspond with the signals at the various leads of FIG. 1. The timing diagram indicates that the circuit is balanced. The rising edge of the clock signal is correctly aligned with the center of an incoming data bit. The width of the UP pulse and the width of the DOWN pulse are also equal, further indicating that data stream and local clock are phase-locked.
FIG. 2 illustrates a prior art phase-locked loop 20 that includes Hogge detector 10. The phase-locked loop 20 is also described in U.S. Pat. No. 4,535,459, as well as U.S. Pat. No. 5,799,048 to Farjad-Rad et al., the entirety of which are incorporated herein by reference. Briefly, the UP and DOWN signals are summed and integrated by charge pump circuit 22, which may be of any conventional design. The charge pump 22 produces a control voltage (Vcontrol) which is inputted to a voltage controlled oscillator (VCO) 24. VCO 24 adjusts the phase of the clock signal in response to the value of Vcontrol. If the clock signal is advanced relative to the center of the data bits of an input data signal, the width of the UP pulse is narrower than the width of the DOWN pulse, causing a negative shift in Vcontrol. VCO 24 then retards the clock signal until Vcontrol indicates that the UP pulse and DOWN pulse have equal widths, and that phase-lock or balance has occurred. Similarly, if the clock signal is retarded with respect to the center of the data bits of an input data signal, the width of the UP pulse is greater than the constant width of the DOWN pulse, causing a positive shift in Vcontrol. VCO 24 then advances the clock signal until Vcontrol indicates that the UP pulse and DOWN pulse have equal widths, and that phase-lock has occurred.
One disadvantage of the Hogge detector is that the flip-flops 12, 14 used in the detector 10 and phase-locked loop 20 need to be very fast. Higher frequency data rates have smaller data bit periods and are thus more sensitive to delays through circuit elements. The flip-flops preferably have a clock-to-Q delay of less than half the clock period. This delay may vary, but for illustrative purposes, this delay is shown in the timing diagram of FIG. 5 as a one-quarter period (T/4) delay at Qup and Qdown. A delay of one-quarter period is also shown in the UP and DOWN waveforms, due to delays through exclusive OR gates 16, 18, respectively. For a 2.5 Gbps system, this half period is 200 ps. To accommodate jitter and other manufacturing margins, this number would be expected to be less than 150 ps. This requirement calls for very fast flip-flops. Such flip-flops, even if the process technology is supportive, consume a great deal of power.
A further disadvantage of the Hogge detector 10 is the need for delay element 24. The delay element 24 is used in the Hogge detector 10 to mimic the clock-to-Q delay of a flip-flop. Such a delay element is required to place the clock edge exactly at the center of an incoming data bit at phase-lock. Without the delay element 24, the clock edges will be a little bit to the left or right of the data edges, resulting in a loss of margin and a greater likelihood that noise will cause an error in recovering the data. Therefore, significant design efforts are expended on the delay element.
Further, the Hogge detector 10 produces narrow UP and DOWN pulses of one half period at phase-lock, as indicated in FIG. 5. Short pulses place greater demands on the response time and ability of the charge pump 22. Further, a loop may be non-responsive to smaller differences between narrow UP and DOWN pulses.
Therefore, there is currently a need to eliminate the dependence of a phase detector on a delay element, as well as reduce the power consumed by the flip-flops of a phase detector. Further, it is desirable to allow the charge pump of a phase-locked loop a longer response time to differences between UP and DOWN pulses, and thus a better response to smaller phase differences between an input data stream and a local clock.
The present invention is a method and apparatus for determining the phase difference between an incoming data stream and a local clock, as well as a method and apparatus for phase aligning a local clock with the incoming data stream. A phase detector for outputting a reference pulse and a variable width pulse indicative of the phase difference between the local clock and the incoming data stream is provided. The phase detector includes a means for frequency dividing the input data signal and a plurality of data latches connected in series. The frequency divided signal is passed through the series of data latches, and signals at the data inputs and data outputs of each data latch are inputted to a first and second exclusive OR gates to provide the variable width pulse and the reference pulse, respectively. The phase detector may also include a fourth data latch clocked with an inverted clock signal to provide a re-timed data signal at its output.
The phase-locked loop according to the present invention includes the above-described phase detector and a charge pump circuit coupled to the outputs of the first and second exclusive OR gates. The charge pump sums and integrates the variable width and reference pulses to provide a control voltage to a voltage controlled oscillator. The voltage controlled oscillator provides the clock signal for clocking the data latches of the phase detector.
The present invention provides several benefits. The phase detector and phase-locked loop function even with set up time plus clock-to-Q delays of a full clock period. This allows for functional designs having slower flip-flops that consume less power The phase-detector of the present invention also performs admirably without a delay element. Further, the phase detector of the present invention produces variable width pulses and reference pulses that are twice as wide as those of the Hogge detector 10, thereby permitting the phase-locked loop to be more responsive to smaller differences in phase between the input data stream and the clock signal. Therefore, the xe2x80x9cdead zone,xe2x80x9d or zone where the difference in phase is too small for the phase loop to respond, is minimized. This feature is very beneficial in circuits designed for high data rates.